R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 655

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 618 of 802
28.4
Figure 28.2
28.4.1
TRAIC register
LINST register
Figure 28.2 shows an Operating Example during Header Field Transmission in master mode. Figures 28.3 and
28.4 show Examples of Header Field Transmission Flowchart.
During header field transmission, the hardware LIN operates as follows:
(1) When 1 is written to the TSTART bit in the TRACR register for timer RA, a low-level signal is output from
(2) When timer RA underflows, the TXD0 pin output is inverted and the SBDCT flag in the LINST register is
(3) The hardware LIN transmits 55h via UART0.
(4) After the hardware LIN completes transmitting 55h, it transmits an ID field via UART0.
(5) After the hardware LIN completes transmitting the ID field, it performs communication for a response
SBDCT flag in
Functional Description
the TXD0 pin for the period set in registers TRAPRE and TRA for timer RA.
set to 1. If the SBIE bit in the LINCR register is set to 1, a timer RA interrupt is generated.
field.
TXD0 pin
IR bit in
Master Mode
Operating Example during Header Field Transmission
1
0
1
0
1
0
The above applies under the following conditions:
LINE = 1, MST = 1, SBIE = 1
Oct 30, 2009
(1)
Synch Break
(2)
(3)
Set to 0 when an interrupt request is acknowledged
or by a program.
1 is written to the B1CLR bit in the LINST register.
Synch Field
(4)
IDENTIFIER
28. Hardware LIN
(5)