R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 564

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 527 of 802
24.5
Table 24.9
Notes:
Transfer data format
Transfer clock
Transmit start conditions
Receive start conditions
Interrupt request generation
timing
Error detection
Selectable functions
I
Specifications. Tables 24.10 and 24.11 list the registers used in I
Mode Functions, Figure 24.13 shows a Block Diagram of I
Register and Interrupt Timing.
As shown in Table 24.12, the MCU is placed in I
to 1. Because SDA2 transmit output has a delay circuit attached, SDA2 output does not change state until SCL2
goes low and remains stably low.
2
1. If an external clock is selected, the requirements must be met while the external clock is held high.
2. If an overrun error occurs, the received data in the U2RB register will be undefined. The IR bit in the S2RIC
C mode is provided for use as a simplified I
register remains unchanged.
Special Mode 1 (I
Item
I
2
C Mode Specifications
Oct 30, 2009
2
Transfer data length: 8 bits
• Master mode
• Slave mode
To start transmission, the following requirements must be met:
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data in the U2TB register).
To start reception, the following requirements must be met:
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data in the U2TB register).
Start/stop condition detection, no acknowledgement detection, or acknowledgement
detection
Overrun error
• SDA2 digital delay
• Clock phase setting
C Mode)
The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n+1))
fj = f1, f8, f32, fC n = Value set in U2BRG register: 00h to FFh
The CKDIR bit is set to 1 (external clock): Input from the SCL2 pin
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles
can be selected.
With or without clock delay can be selected.
This error occurs if the serial interface starts receiving the next unit of data before
reading the U2RB register and receives the 8th bit of the next unit of data.
(2)
2
2
C mode by setting bits SMD2 to SMD0 to 010b and the IICM bit
C interface compatible mode. Table 24.9 lists the I
2
C Mode, and Figure 24.14 shows the Transfer to U2RB
2
C mode and the settings. Table 24.12 lists the I
Specification
24. Serial Interface (UART2)
(1)
(1)
2
C Mode
2
C