R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 449

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 412 of 802
20.8.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM3 Mode
20.8.13 Timer RD Counter 0 (TRD0) in PWM3 Mode
b15 to b0 A count source is counted. Count operation is increment.
After Reset
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Address 0144h (TRDIER0), 0154h (TRDIER1)
Address 0147h to 0146h
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
The TRD1 register is not used in PWM3 mode.
Symbol
Symbol
Symbol
Symbol
Bit
IMIEA
IMIEB
IMIEC
IMIED
Bit
Bit
OVIE
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
—
—
—
b15
b7
b7
—
—
—
1
0
0
Input-capture/compare-match interrupt
enable bit A
Input-capture/compare-match interrupt
enable bit B
Input-capture/compare-match interrupt
enable bit C
Input-capture/compare-match interrupt
enable bit D
Overflow/underflow interrupt enable bit 0: Interrupt (OVI) by OVF bit disabled
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
b14
b6
b6
—
—
—
1
0
0
Oct 30, 2009
Bit Name
b13
b5
—
b5
—
—
1
0
0
Function
OVIE
b12
b4
b4
—
—
0
0
0
IMIED
0: Interrupt (IMIA) by IMFA bit disabled
1: Interrupt (IMIA) by IMFA bit enabled
0: Interrupt (IMIB) by IMFB bit disabled
1: Interrupt (IMIB) by IMFB bit enabled
0: Interrupt (IMIC) by IMFC bit disabled
1: Interrupt (IMIC) by IMFC bit enabled
0: Interrupt (IMID) by IMFD bit disabled
1: Interrupt (IMID) by the IMFD bit enabled
1: Interrupt (OVI) by OVF bit enabled
b11
b3
b3
—
—
0
0
0
IMIEC
b10
b2
b2
—
—
0
0
0
Function
IMIEB
b1
b1
b9
—
—
0
0
0
0000h to FFFFh
IMIEA
Setting Range
b0
b0
b8
—
—
0
0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—