R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 497

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 460 of 802
22.4.1
Notes:
1. When the IOA2 bit is set to 1 (input capture function), the TRGGRA register functions as an input capture
2. When the IOB2 bit is set to 1 (input capture function), the TRGGRB register functions as an input capture
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0175h
register.
register.
Symbol
Symbol
Bit
BUFB
BUFA
IOA0
IOA1
IOA2
IOB0
IOB1
IOB2
Timer RG I/O Control Register (TRGIOR) in Timer Mode (Input Capture
Function)
BUFB
b7
0
TRGGRA control bit
TRGGRA mode select bit
TRGGRC register function
select bit
TRGGRB control bit
TRGGRB mode select bit
TRGGRD register function
select bit
IOB2
b6
Bit Name
0
Oct 30, 2009
IOB1
b5
0
(1)
(2)
IOB0
b1 b0
Set to 1 (input capture) for the input capture function.
0: Not used as the buffer register of the TRGGRA register
1: Used as the buffer register of the TRGGRA register
b5 b4
Set to 1 (input capture) for the input capture function.
0: Not used as the buffer register of the TRGGRB register
1: Used as the buffer register of the TRGGRB register
b4
0 0: Input capture to TRGGRA at the rising edge
0 1: Input capture to TRGGRA at the falling edge
1 0: Input capture to TRGGRA at both edges
1 1: Do not set.
0 0: Input capture to TRGGRB at the rising edge
0 1: Input capture to TRGGRB at the falling edge
1 0: Input capture to TRGGRB at both edges
1 1: Do not set.
0
BUFA
b3
0
IOA2
b2
0
Function
IOA1
b1
0
IOA0
b0
0
22. Timer RG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W