R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 522

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 485 of 802
23.3
Table 23.2
i = 0 or 1
Notes:
Transfer data format
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
Selectable functions
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 23.2 lists the Clock Synchronous Serial I/O Mode Specifications. Table 23.3 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode
1. When an external clock is selected, the requirements must be met in either of the following states:
2. If an overrun error occurs, the receive data (b0 to b8) in the UiRB register will be undefined.
- The external clock is held high when the CKPOL bit in the UiC0 register is set to 0 (transmit data
- The external clock is held low when the CKPOL bit in the UiC0 register is set to 1 (transmit data
The IR bit in the SiRIC register remains unchanged.
Clock Synchronous Serial I/O Mode
output at the falling edge and receive data input at the rising edge of the transfer clock)
output at the rising edge and receive data input at the falling edge of the transfer clock)
Item
Clock Synchronous Serial I/O Mode Specifications
Oct 30, 2009
• Transfer data length: 8 bits
• The CKDIR bit in the UiMR register is set to 0 (internal clock): fi/(2(n+1))
• The CKDIR bit is set to 1 (external clock): Input from the CLKi pin
• To start transmission, the following requirements must be met:
• To start reception, the following requirements must be met:
• For transmission, one of the following can be selected.
• For reception
• Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
fi = f1, f8, f32, fC n = Value set in UiBRG register: 00h to FFh
- The TE bit in the UiC1 register is set to 1 (transmission enabled).
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register).
- The RE bit in the UiC1 register is set to 1 (reception enabled).
- The TE bit in the UiC1 register is set to 1 (transmission enabled).
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register).
- The UiIRS bit is set to 0 (transmit buffer empty):
- The UiIRS bit is set to 1 (transmission completed):
When data is transferred from the UARTi receive register to the UiRB
register (at completion of reception).
This error occurs if the serial interface starts receiving the next unit of data
before reading the UiRB register and receives the 7th bit of the next unit of
data.
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
Whether data transmission/reception begins with bit 0 or begins with bit 7
can be selected.
Reception is enabled immediately by reading the UiRB register.
When data is transferred from the UiTB register to the UARTi transmit
register (at start of transmission).
When data transmission from the UARTi transmit register is completed.
(2)
(1)
.
Specification
23. Serial Interface (UARTi (i = 0 or 1))
(1)
(1)