R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 853

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1.00
Rev.
REVISION HISTORY
Oct 30, 2009
Date
678 to 689 Figure 32.6 to Figure 32.29
459, 463,
476, 771 22.9.2, 35.12.2 Timer RG Counter (TRG) added
651, 774 29.10, 35.18 “Do not select fOCO-F as AD.”, “
690, 775 32.6.1, 32.6.2, 35.19.1, 35.19.2 revised
Page
450
452
455
458
467
489
491
496
497
499
523
524
619
622
629
630
633
655
662
663
664
667
672
675
696
679
22.2.5 Note 2, “When reading the TRGSR register...for writing and reading.” added
22.2.7 “This register operates incrementing and ...”
Table 22.4, Figure 22.2 “f2”, “fOCO40M” deleted
Figure 22.5 “f2”, “fOCO40M” deleted
Table 22.6 to Table 22.8 “f2”, “fOCO40M” deleted
23.3.1 Measure for Dealing with Communication Errors added
Table 23.5 Error detection revised
Table 23.8 Note 1 deleted
23.4.2 “(2) Reset bits SMD2 to SMD0 in the UiMR register to 001b, ...”
24.1 “UART2 has a dedicated timer to ... operate independently.”
Table 24.8 Note 1 deleted
24.4.2 “(2) Reset bits SMD2 to SMD0 in the U2MR register to 001b, ...”
Figure 28.3 “fOCO”
Figure 28.6 “fOCO”
Table 29.1 “or fOCO-F” deleted
Figure 29.1 revised
29.2.3 b2 revised, Note 1 deleted
CKS2 bit in the ADMOD register while fOCO-F is stopped.” deleted
“The last 32. Comparator A” deleted
Table 32.1 revised
Table 32.2 “Maximum number of display pixels” added,
“LCD drive timing” revised, “Bias control” revised,
“LCD display data register” revised
Table 32.3 revised, Figure 32.1 revised
32.2.3 b4, 32.2.4 b0 to b2 revised
32.3 “(turned on/off or inverted)”
32.4.1 “... LSEi bit (i = 00 to 59) bit to ...”
32.4.3 revised
“LCD base clock (Internal signal)”
Figure 32.8 revised
Table 33.3 “CPU state during programming and block erasure”
R8C/L35A Group, R8C/L35B Group, R8C/L36A Group, R8C/L36B Group, R8C/L38A Group,
R8C/L38B Group, R8C/L3AA Group, R8C/L3AB Group Hardware Manual
“(2) Reset bits SMD2 to SMD0 in the UiMR register to 100b, ...”
“UART2 has a dedicated timer to ... operate.”
“(2) Reset bits SMD2 to SMD0 in the U2MR register to 100b, ...”
“CPU and DTC states during programming and block erasure”
“This register operates incrementing/decrementing and ...”
C - 14
“fOCO-S”
“fOCO-S”
Description
Summary
“(blink or invert)”
“Internal signal LCDCK timing”
“... LSEi bit (i = 00 to 59) to...”
•
Do not change the