R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 601

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 564 of 802
Figure 26.5
26.4.2
Figure 26.5 shows an Example of Synchronous Serial Communication Unit Operation during Data
Transmission (Clock Synchronous Communication Mode, 8-Bit SSU Data Transfer Length). During data
transmission, the synchronous serial communication unit operates as described below (the data transfer length
can be set from 8 to 16 bits using the SSBR register).
When the synchronous serial communication unit is set as the master device, it outputs a synchronous clock and
data. When the synchronous serial communication unit is set as a slave device, it outputs data synchronized
with the input clock.
When the TE bit is set to 1 (transmission enabled) before writing the transmit data to the SSTDR register, the
TDRE bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is
transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data transferred from registers
SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1 at this time, a TXI
interrupt request is generated.
When one frame of data is transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR
to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set
to 1, the TEND bit in the SSSR register is set to 1 (TDRE bit is set to 1 when the last bit of the transmit data is
transmitted) and the state is retained. When the TEIE bit in the SSER register is set to 1 (transmit-end interrupt
request enabled) at this time, a TEI interrupt request is generated. The SSCK pin is fixed high after transmit-
end.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
Figure 26.6 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode).
TDRE bit in
SSSR register
TEND bit in
SSSR register
Program
processing
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at odd edges),
Data Transmission
CPOS = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits)
Transmission (Clock Synchronous Communication Mode, 8-Bit SSU Data Transfer
Length)
Example of Synchronous Serial Communication Unit Operation during Data
SSCK
SSO
1
0
1
0
Write data to the SSTDR register.
Oct 30, 2009
TXI interrupt request generation
b0
b1
1 frame
b7
26. Synchronous Serial Communication Unit (SSU)
b0
TEI interrupt request
generation
BS0 to BS3: Bits in SSBR register
CPHS, CPOS: Bits in SSMR register
SSUMS: Bit in SSMR2 register
b1
1 frame
b7