R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 544

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 507 of 802
24.2.9
Note:
24.2.10 UART2 Special Mode Register 3 (U2SMR3)
Notes:
1. This bit is set to 0 when the condition is generated.
1. Bits DL2 to DL0 are used to generate a delay in SDA2 output digitally in I
2. The amount of delay varies with the load on pins SCL2 and SDA2. When an external clock is used, the amount
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00BCh
Address 00BDh
these bits to 000b (no delay).
of delay increases by about 100 ns.
Symbol
Symbol
RSTAREQ Restart condition generate bit
STSPSEL SCL, SDA output select bit
STPREQ Stop condition generate bit
STAREQ Start condition generate bit
Symbol
NODC
Bit
Symbol
Bit
CKPH
SCLHI
SWC9
ACKD
ACKC
DL0
DL1
DL2
UART2 Special Mode Register 4 (U2SMR4)
—
—
—
SWC9
DL2
b7
b7
0
0
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
Clock phase set bit
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
Clock output select bit
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
SDA2 digital delay setup bit
ACK data bit
ACK data output enable bit
SCL output stop enable bit
SCL wait bit 3
SCLHI
DL1
b6
b6
0
0
Oct 30, 2009
Bit Name
Bit Name
ACKC
DL0
b5
b5
0
0
(1, 2)
ACKD
(1)
(1)
b4
b4
—
X
0
(1)
STSPSEL STPREQ RSTAREQ STAREQ
0: No clock delay
1: With clock delay
0: CLK2 set as CMOS output
1: CLK2 set as N-channel open-drain output
b7 b6 b5
NODC
0 0 0: No delay
0 0 1: 1 or 2 cycles of U2BRG count source
0 1 0: 2 or 3 cycles of U2BRG count source
0 1 1: 3 or 4 cycles of U2BRG count source
1 0 0: 4 or 5 cycles of U2BRG count source
1 0 1: 5 or6 cycles of U2BRG count source
1 1 0: 6 or 7 cycles of U2BRG count source
1 1 1: 7 or 8 cycles of U2BRG count source
0: Clear
1: Start
0: Clear
1: Start
0: Clear
1: Start
0: Start and stop conditions not output
1: Start and stop conditions output
0: ACK
1: NACK
0: Serial interface data output
1: ACK data output
0: Disabled
1: Enabled
0: SCL hold low disabled
1: SCL hold low enabled
b3
b3
0
0
b2
b2
—
X
0
2
Function
CKPH
Function
C mode. In other than I
b1
0
b1
0
24. Serial Interface (UART2)
b0
—
X
b0
0
2
C mode, set
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—