R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 232

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 195 of 802
14.3
Figure 14.2
14.3.1
Count starts
14.3.1.1
0%
Note:
1. A watchdog timer interrupt or watchdog timer reset is generated.
The period for acknowledging refreshment operation to the watchdog timer (write to the WDTR register) can
be selected by bits WDTRCS0 and WDTRCS1 in the OFS2 register. Figure 14.2 shows the Refresh
Acknowledgement Period for Watchdog Timer.
Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, a refresh
operation executed during the refresh acknowledgement period is acknowledged. Any refresh operation
executed during the period other than the above is processed as an incorrect write, and a watchdog timer
interrupt or watchdog timer reset (selectable by the PM12 bit in the PM1 register) is generated.
Do not execute any refresh operation while the count operation of the watchdog timer is stopped.
Processed as
incorrect write
Processed as incorrect write
Functional Description
Common Items for Multiple Modes
Processed as incorrect write
Refresh Acknowledgment Period
Refresh Acknowledgement Period for Watchdog Timer
25%
(1)
Refresh can be acknowledged
Watchdog timer period
Refresh can be acknowledged
(1)
Oct 30, 2009
50%
Refresh can be acknowledged
(1)
75%
Refresh can be
acknowledged
Underflow
100%
Refresh acknowledge period
100% (WDTRCS1 to WDTRCS0 = 11b)
75% (WDTRCS1 to WDTRCS0 = 10b)
50% (WDTRCS1 to WDTRCS0 = 01b)
25% (WDTRCS1 to WDTRCS0 = 00b)
WDTRCS0, WDTRCS1: Bits in OFS2 register
14. Watchdog Timer