R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 257

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 220 of 802
17. Timer RA
17.1
Figure 17.1
The description offered in this chapter is based on the R8C/L3AA Group and the R8C/L3AB Group.
For other groups, refer to 1.1.2 Differences between Groups.
Table 17.1
TRAIO pin
TRAO pin
TRAIO
TRAO
Timer RA is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated
at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 17.2 to 17.6
the Specifications of Each Mode).
The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 17.1 shows the Timer RA Block Diagram. Table 17.1 lists the Timer RA Pin Configuration.
Timer RA supports the following five operating modes:
• Timer mode:
• Pulse output mode:
• Event counter mode:
• Pulse width measurement mode:
• Pulse period measurement mode:
Note
Pin Name
Note:
1. The POL bit in the INT2IC register is used to select the INT2 level when the event input is enabled.
Introduction
f32
f1
f8
Bits TIPF1 to TIPF0
fOCO-S
Event input enabled for “L” period of
Event input enabled at INT2 level
Bits TCK2 to TCK0
= 01b
= 10b
= 11b
fC32
fC
f1
f8
f2
Timer RA Block Diagram
Timer RA Pin Configuration
Event input always enabled
= 000b
= 001b
= 010b
= 011b
= 100b
= 110b
TRCIOD (timer RC output)
P11_4
P11_5
Digital
filter
Assigned Pin
TOENA bit
Bits TIPF1 to TIPF0
= other than 000b
= 00b
Oct 30, 2009
Bits TIOGT1 to TIOGT0
(3)
= 00b
= 01b
= 10b
switching
Polarity
Bits TMOD2 to TMOD0
Bits TMOD2 to TMOD0
= other than 010b
The timer counts an internal count source.
the polarity by underflow of the timer.
The timer counts an internal count source and outputs pulses which invert
The timer counts external pulses.
The timer measures the pulse width of an external pulse.
The timer measures the pulse period of an external pulse.
Bits TMOD2 to TMOD0 = 001b
TOPCR bit
Output
= 010b
I/O
I/O
TCSTF, TSTOP: Bits in TRACR register
TEDGSEL, TOPCR, TOENA, TIPF1, TIPF0, TIOGT1, TIOGT0: Bits in TRAIOC register
TMOD0 to TMOD2, TCK0 to TCK2, TCKCUT: Bits in TRAMR register
Bits TMOD2 to TMOD0
TCKCUT
Function differs according to the mode.
Refer to descriptions of individual modes for details.
bit
= 011b or 100b
TEDGSEL = 1
TEDGSEL = 0
TCSTF
Count control
bit
circuit
TRAPRE register
Q
Q
register
Reload
(prescaler)
Counter
flip-flop
Toggle
Measurement end signal
CLR
Data bus
CK
Function
register
Reload
Write to TRAMR register
Write 1 to TSTOP bit
TRA register
Counter
(timer)
Underflow signal
Timer RA interrupt
17. Timer RA