R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 362

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 325 of 802
20.3.11 Timer RD Status Register i (TRDSRi) (i = 0 or 1) for Input Capture Function
Notes:
1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1.
2. The results of writing to these bits are as follows:
3. Edge selected by bits IOj0 and IOj1 (j = A or B) in the TRDIORAi register.
4. Edge selected by bits IOk0 and IOk1 (k = C or D) in the TRDIORCi register.
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0143h (TRDSR0), 0153h (TRDSR1)
• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is
• The bit’s value remains unchanged if 1 is written to it.
Including when the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as a buffer register)
Symbol
retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it
because its previous value is retained.)
Symbol
Bit
IMFB
IMFC
IMFD
IMFA
OVF
UDF
—
—
b7
—
1
1
Input-capture/compare-match flag A
Input-capture/compare-match flag B
Input-capture/compare-match flag C [Condition for setting this bit to 0]
Input-capture/compare-match flag D [Condition for setting this bit to 0]
Overflow flag
Underflow flag
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
b6
—
1
1
Oct 30, 2009
Bit Name
(1)
UDF
b5
1
0
OVF
b4
0
0
[Condition for setting this bit to 0]
Write 0 after reading.
[Condition for setting this bit to 1].
TRDSR0 register:
TRDSR1 register:
[Condition for setting this bit to 0]
Write 0 after reading.
[Condition for setting this bit to 1]
Input edge of TRDIOBi pin
Write 0 after reading.
[Condition for setting this bit to 1]
Input edge of TRDIOCi pin
Write 0 after reading.
[Condition for setting this bit to 1]
Input edge of TRDIODi pin
[Condition for setting this bit to 0]
Write 0 after reading.
[Condition for setting this bit to 1]
When the TRDi register overflows.
Disabled for the input capture function.
fOCO128 signal edge when the IOA3 bit in the
TRDIORA0 register is set to 0 (fOCO128 signal).
Input edge of TRDIOA0 pin when the IOA3 bit in
the TRDIORA0 register is set to 1 (TRDIOA0
input)
Input edge of TRDIOA1 pin
IMFD
b3
0
0
(3)
.
IMFC
b2
0
0
Function
(2)
(2)
(2)
(2)
(2)
IMFB
b1
0
0
(3)
(4)
(4)
(3)
.
.
.
.
IMFA
b0
0
0
TRDSR0 register
TRDSR1 register
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—