R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 312

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 275 of 802
Figure 19.5
19.3.3
(or TRCTRG input signal)
TRCIOj input signal
signal)
(or TRCTRG input
TRCIOj input signal
TRCCLK
The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is determined when three
matches occur. The digital filter function and sampling clock can be selected using the TRCDF register.
Figure 19.5 shows a Block Diagram of Digital Filter.
Input signal after
passing through
Sampling clock
f32
f1
f2
f4
f8
digital filter
Digital Filter
TCK0 to TCK2: Bits in TRCCR1 register
DFTRG, DFCK0, DFCK1, DFj: Bits in TRCDF register
IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register
IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register
TCEG0, TCEG1: Bits in TRCCR2 register
j = A, B, C, or D
Clock cycle selected by
= 011b
= 100b
Block Diagram of Digital Filter
Timer RC operating clock
(or DFCK1 to DFCK0)
= 010b
= 101b
TCK2 to TCK0
D
D
= 001b
Latch
Latch
C
TCK2 to TCK0
f1
C
Q
Q
= 000b
Count source
Oct 30, 2009
D
f32
f8
f1
Latch
C
If fewer than three matches occur,
the matches are recognized as noise
and no transmission is performed.
= 01b
= 10b
= 00b
DFCK1 to DFCK0
= 11b
Q
D
Latch
C
Sampling clock
Q
D
Latch
C
Q
Match detect
Maximum signal transmission
delay is five sampling clocks.
circuit
a signal change is confirmed.
Three matches occur and
DFj (or DFTRG)
1
0
(or TCEG1 to TCEG0)
IOA2 to IOA0
IOB2 to IOB0
IOC2 to IOC0
IOD2 to IOD0
Edge detect
circuit
19. Timer RC