R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 643

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 606 of 802
Figure 27.14
27.5.2
In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the
transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when
the MST bit is set to 0.
Figure 27.14 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode).
The transmit procedure and operation in transmit mode are as follows:
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Then set bits CKS0 to CKS3 in the
(2) Set the TRS bit in the ICCR1 register to 1 to select transmit mode. This will set the TDRE bit in the ICSR
(3) After confirming that the TDRE bit is set to 1, write transmit data to the ICDRT register. Data is transferred
Program processing
ICDRT register
ICDRS register
ICCR1 register
ICCR1 register and the MST bit (initial setting).
register is to 1.
from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1. Continuous transmission is
enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. To switch from transmit
to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1.
ICSR register
TDRE bit in
Transmit Operation
TRS bit in
(output)
SDA
SCL
Operating Timing in Transmit Mode (Clock Synchronous Serial Mode)
(2) Set the TRS bit to 1.
1
0
1
0
(3) Write data to
the ICDRT register.
Oct 30, 2009
Data 1
b0
Data 1
1
b1
(3) Write data to
2
the ICDRT register.
b6
Data 2
7
b7
8
b0
Data 2
1
(3) Write data to
b6
the ICDRT register.
7
b7
8
(3) Write data to
Data 3
Data 3
the ICDRT register.
27. I
b0
1
2
C bus Interface