R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 593

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 556 of 802
26.2.10 SS Status Register (SSSR)
Notes:
1. Writing 1 to the CE, ORER, RDRF, TEND, or TDRE bit is disabled. To set any of these bits to 0, first read 1 then
2. When the serial communication is started while the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
3. Indicates when an overrun error occurs during reception and completes in error. If the next serial data receive
4. The RDRF bit is set to 0 when reading the data from the SSRDR register.
5. Bits TEND and TDRE are set to 0 when writing data to the SSTDR register.
6. The TDRE bit is set to 1 when the TE bit in the SSER register is set to 1 (transmission enabled).
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 019Ch
write 0.
communication mode) and the MSS bit in the SSCRH register is set to 1 (operation as the master device), the
CE bit is set to 1 if a low-level signal is applied to the SCS pin input. Refer to 26.5.4 SCS Pin Control and
Arbitration for more information.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode), the MSS bit in the
SSCRH register is set to 0 (operation as a slave device) and the SCS pin input changes the level from low to
high during transfer, the CE bit is set to 1.
operation is completed while the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1.
After the ORER bit is set to 1 (overrun error), receive operation is disabled while the bit remains 1. Transmit
operation is also disabled while the MSS bit is set to 1 (operation as the master device).
To access the SSSR register successively, insert one or more NOP instructions between the instructions used for
access.
Symbol
Symbol
ORER
Bit
RDRF
TEND
TDRE
CE
—
—
—
TDRE
b7
0
Conflict error flag
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Overrun error flag
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Receive data register full flag
Transmit end flag
Transmit data empty flag
TEND
b6
0
Oct 30, 2009
Bit Name
(1)
RDRF
(1, 5)
(1)
b5
0
(1, 5, 6)
(1, 4)
b4
—
0
0: No conflict error
1: Conflict error
0: No overrun error
1: Overrun error
0: No data in the SSRDR register
1: Data in the SSRDR register
0: TDRE bit is set to 0 when transmitting the last bit of
1: TDRE bit is set to 1 when transmitting the last bit of
0: No data transferred from registers SSTDR to
1: Data transferred from registers SSTDR to SSTRSR
transmit data
transmit data
SSTRSR
b3
—
0
26. Synchronous Serial Communication Unit (SSU)
ORER
(2)
b2
(3)
0
Function
b1
—
0
CE
b0
0
R/W
R/W
R/W
R/W
R/W
R/W
—
—