R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 273

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 236 of 802
17.8
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time in the
• In pulse width measurement mode and pulse period measurement mode, bits TEDGF and TUNDF in the TRACR
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
• The TCSTF bit remains 0 (count stops) for zero or one cycle of the count source after setting the TSTART bit to
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or
starts.
MCU. Consequently, the timer value may be updated during the period when these two registers are being read.
register can be set to 0 by writing 0 to these bits by a program. However, these bits remain unchanged if 1 is
written. When using the READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF
bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to
the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
immediately after the count starts, then set the TEDGF bit to 0.
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RA
counting at the first active edge of the count source after the TCSTF bit is set to 1 (during count operation).
The TCSTF bit remains 1 for zero or one cycle of the count source after setting the TSTART bit to 0 (count stops)
while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA
Note:
more cycles of the count source clock for each write interval.
more cycles of the prescaler underflow for each write interval.
1. Registers associated with timer RA:
Notes on Timer RA
TRACR, TRAIOC, TRAMR, TRAPRE, and TRA
Oct 30, 2009
(1)
(1)
other than the TCSTF bit.
other than the TCSTF bit. Timer RA starts
17. Timer RA