R5F2L3AAANFP#U1 Renesas Electronics America, R5F2L3AAANFP#U1 Datasheet - Page 432

• Manufacturer Part Number: R5F2L3AAANFP#U1
• Description: MCU FLASH 96+4KB 100LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3AAANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 395 of 802
20.7.13 Timer RD Counter 1 (TRD1) in Complementary PWM Mode
20.7.14 Timer RD General Registers Ai, Bi, C1, and Di (TRDGRAi, TRDGRBi,
b15 to b0 Set 0000h.
b15 to b0 Refer to Table 20.14 TRDGRji Register Functions in Complementary PWM Mode
After Reset
After Reset
After Reset
After Reset
Bit
Bit
Address 0157h to 0156h
Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0),
Access the TRD1 register in 16-bit units. Do not access it in 8-bit units.
Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
The TRDGRC0 register is not used in complementary PWM mode.
The following registers are disabled in complementary PWM mode:
TRDPMR, TRDOCR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1,
TRDIORC1, and TRDPOCR1.
Symbol
Symbol
Symbol
Symbol
Bit
Bit
Bit
Bit
A count source is counted. Count operation is increment or decrement.
When an underflow occurs, the UDF bit in the TRDSR1 register is set to 1.
TRDGRC1, TRDGRDi) (i = 0 or 1) in Complementary PWM Mode
014Fh to 014Eh (TRDGRD0),
0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1),
015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1)
b15
b15
b7
b7
—
—
—
—
0
0
1
1
b14
b14
b6
b6
—
—
—
—
0
0
1
1
Oct 30, 2009
b13
b13
b5
—
—
b5
—
—
0
0
1
1
Function
b12
b12
b4
b4
—
—
—
—
0
0
1
1
Function
b11
b11
b3
b3
—
—
—
—
0
0
1
1
b10
b10
b2
b2
—
—
—
—
0
0
1
1
b1
b9
b1
b9
—
—
—
—
0
0
1
1
0000h to FFFFh
Setting Range
b0
b8
b0
b8
—
—
—
—
0
0
1
1
20. Timer RD
R/W
R/W
R/W
R/W