LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1012
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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<Document ID>
User manual
42.5.5.2 Base clock status register
Each bit in this register indicates if the specified base clock can be safely switched off. A
logic zero indicates that all branch clocks generated from this base clock are disabled.
Hence, the base clock can also be switched off. A logic one value indicates that there is
still at least one branch clock running.
Remark: The base clock must be reactivated before writing to the configuration register of
the branch clock.
Table 957. CCU1 base clock status register (CCU1_BASE_STAT, address 0x4005 1004) bit
Table 958. CCU2 base clock status register (CCU2_BASE_STAT, address 0x4005 2004) bit
Bit
0
1
2
3
6:4
7
8
31:9 -
Bit
0
1
2
Symbol
BASE_APB3_
CLK_IND
BASE_APB1_
CLK_IND
BASE_SPIFI_
CLK_IND
BASE_M3_
CLK_IND
-
BASE_USB0_
CLK_IND
BASE_USB1_
CLK_IND
Symbol
-
BASE_UART3_
CLK
BASE_UART2_
CLK
description
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Reserved.
Base clock indicator for BASE_UART3_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_UART2_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Description
Base clock indicator for BASE_APB3_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_APB1_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_SPIFI_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_M3_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Reserved
Base clock indicator for BASE_USB0_CLK
0 = All branch clocks switched off.
1 = At least one branch clock running.
Base clock indicator for BASE_USB1_CLK
0 = All branch clocks switched off.
1 = at least one branch clock running.
Reserved
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
1
1
1
1
-
1
1
-
Reset
value
-
1
1
1012 of 1164
Access
R
R
R
R
-
R
R
-
Access
-
R
R
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