LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1064

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 992. Pin description
<Document ID>
User manual
Pin name
I2S_RX_SCK
I2S_RX_WS
I2S_RX_SDA
I2S_RX_MCLK
I2S_TX_SCK
I2S_TX_WS
I2S_TX_SDA
IS_TX_MCLK
42.9.5 Pin description
Direction
Input/
Output
Input/
Output
Input/
Output
Output
Input/
Output
Input/
Output
Input/
Output
Output
Description
Receive Clock. A clock signal used to synchronize the transfer of data on the receive
channel. It is driven by the master and received by the slave. Corresponds to the signal SCK
in the I2S bus specification.
Receive Word Select. Selects the channel from which data is to be received. It is driven by
the master and received by the slave. Corresponds to the signal WS in the I2S bus
specification.
WS = 0 indicates that data is being received by channel 1 (left channel).
WS = 1 indicates that data is being received by channel 2 (right channel).
Receive Data. Serial data, received MSB first. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S bus specification.
Optional master clock output for the I2S receive function.
Transmit Clock. A clock signal used to synchronize the transfer of data on the transmit
channel. It is driven by the master and received by the slave. Corresponds to the signal SCK
in the I2S bus specification.
Transmit Word Select. Selects the channel to which data is being sent. It is driven by the
master and received by the slave. Corresponds to the signal WS in the I2S bus specification.
WS = 0 indicates that data is being sent to channel 1 (left channel).
WS = 1 indicates that data is being sent to channel 2 (right channel).
Transmit Data. Serial data, sent MSB first. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S bus specification.
Optional master clock output for the I2S transmit function.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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