LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 873

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
37.10.1 Master Transmitter mode
Table 816. Abbreviations used to describe an I
In
set. The numbers in the circles show the status code held in the STAT register. At these
points, a service routine must be executed to continue or complete the serial transfer.
These service routines are not critical since the serial transfer is suspended until the serial
interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in STAT is used to branch to the
appropriate service routine. For each status code, the required software action and details
of the following serial transfer are given in tables from
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver
(see
initialized as follows:
Table 817. CONSET used to initialize Master Transmitter mode
The I
to logic 1 to enable the I
its own slave address or the General Call address in the event of another device
becoming master of the bus. In other words, if AA is reset, the I
slave mode. STA, STO, and SI must be reset.
Abbreviation
S
SLA
R
W
A
A
Data
P
Bit
Symbol
Value
Figure 140
Figure
2
C rate must also be configured in the SCLL and SCLH registers. I2EN must be set
7
-
-
140). Before the master transmitter mode can be entered, CON must be
to
All information provided in this document is subject to legal disclaimers.
Figure
6
I2EN
1
Rev. 00.13 — 20 July 2011
Explanation
START Condition
7-bit slave address
Read bit (HIGH level at SDA)
Write bit (LOW level at SDA)
Acknowledge bit (LOW level at SDA)
Not acknowledge bit (HIGH level at SDA)
8-bit data byte
STOP condition
144, circles are used to indicate when the serial interrupt flag is
2
C block. If the AA bit is reset, the I
5
STA
0
4
STO
0
2
C operation
Chapter 37: LPC18xx I2C-bus interface
3
SI
0
Table 818
2
C block will not acknowledge
2
AA
x
2
C interface cannot enter
to
Table
UM10430
-
1
-
© NXP B.V. 2011. All rights reserved.
824.
873 of 1164
0
-
-