LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 523

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.8.2.5 Reception
The driver must explicitly issue a Transmit Poll Demand command after rectifying the
suspension cause.
The Receive DMA engine’s reception sequence is shown in
follows:
10. The Receive DMA exits the Suspend state when a Receive Poll demand is given or
1. The host sets up Receive descriptors (RDES0-RDES3) and sets the Own bit
2. Once the SR (DMA Operation Mode register
3. The DMA decodes the receive data buffer address from the acquired descriptors.
4. Incoming frames are processed and placed in the acquired descriptor’s data buffers.
5. When the buffer is full or the frame transfer is complete, the Receive engine fetches
6. If the current frame transfer is complete, the DMA proceeds to Step 7. If the DMA
7. If IEEE 1588 time stamping is enabled, the DMA writes the timestamp (if available) to
8. The Receive engine checks the latest descriptor’s Own bit. If the host owns the
9. Before the Receive engine enters the Suspend state, partial frames are flushed from
(RDES0[31]).
Run state. While in the Run state, the DMA polls the Receive Descriptor list,
attempting to acquire free descriptors. If the fetched descriptor is not free (is owned by
the host), the DMA enters the Suspend state and jumps to Step 9.
the next descriptor.
does not own the next fetched descriptor and the frame transfer is not complete (EOF
is not yet transferred), the DMA sets the Descriptor Error bit in the RDES0 (unless
flushing is disabled). The DMA closes the current descriptor (clears the Own bit) and
marks it as intermediate by clearing the Last Segment (LS) bit in the RDES0 value
(marks it as Last Descriptor if flushing is not disabled), then proceeds to Step 8. If the
DMA does own the next descriptor but the current frame transfer is not complete, the
DMA closes the current descriptor as intermediate and reverts to Step 4.
the current descriptor’s RDES2 and RDES3. It then takes the receive frame’s status
from the MTL and writes the status word to the current descriptor’s RDES0, with the
Own bit cleared and the Last Segment bit set.
descriptor (Own bit is 0) the Receive Buffer Unavailable bit (DMA Status register
Table
the DMA owns the descriptor, the engine returns to Step 4 and awaits the next frame.
the Receive FIFO (You can control flushing using Bit 24 of DMA Operation MOde
register
the start of next frame is available from the MTL’s Receive FIFO. The engine
proceeds to Step 2 and refetches the next descriptor.
427) is set and the DMA Receive engine enters the Suspended state (Step 9). If
Table
All information provided in this document is subject to legal disclaimers.
428).
Rev. 00.13 — 20 July 2011
Table
428) bit is set, the DMA enters the
Chapter 22: LPC18xx Ethernet
Figure 49
UM10430
and proceeds as
© NXP B.V. 2011. All rights reserved.
523 of 1164