LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 439

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
21.6 Register description
Table 361. Register overview: USB1 host/device controller (register base address 0x4000 7000)
<Document ID>
User manual
Name
-
Device/host capability registers
CAPLENGTH
HCSPARAMS
HCCPARAMS
DCIVERSION
DCCPARAMS
-
Device/host operational registers
USBCMD_D
USBCMD_H
USBSTS_D
USBSTS_H
USBINTR_D
USBINTR_H
FRINDEX_D
FRINDEX_H
-
DEVICEADDR
PERIODICLISTBASE
ENDPOINTLISTADDR
ASYNCLISTADDR
Remark: For Full-speed operation with on-chip Full-speed PHY, the pads of the PHY
need to be configured. For configuration of these pads see
DP1/DM1
Remark: For operations with an external PHY connected through the ULPI interface the
interface needs to be selected in the PTS bits of the PORTSC1 register
Table 360. Register access abbreviations
Abbreviation
R/W
R/WC
R/WO
RO
WO
Access Address
-
RO
RO
RO
RO
RO
-
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
-
R/W
R/W
R/W
R/W
pins”.
offset
0x000 -
0x0FF
0x100
0x104
0x108
0x120
0x124
0x128 -
0x13C
0x140
0x140
0x144
0x144
0x148
0x148
0x14C
0x14C
0x150
0x154
0x154
0x158
0x158
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Reserved
Capability register length
Host controller structural parameters
Host controller capability parameters
Device interface version number
Device controller capability parameters 0x0000 0184
Reserved
USB command (device mode)
USB command (host mode)
USB status (device mode)
USB status (host mode)
USB interrupt enable (device mode)
USB interrupt enable (host mode)
USB frame index (device mode)
USB frame index (host mode)
Reserved
Frame list base address
Address of endpoint list in memory
(device mode)
Address of endpoint list in memory
(host mode)
USB device address
Chapter 21: LPC18xx USB1 Host/Device controller
Description
Read/Write
Read/Write one to Clear
Read/Write Once
Read Only
Write Only
Section 19.3.4 “USB1
Reset value
0x0001 0040
0x0001 0011
0x0000 0005
0x0000 0001
0x0004 0000
0x0004 00B0
0x0000 0000
0x0000 1000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
UM10430
© NXP B.V. 2011. All rights reserved.
(Section
439 of 1164
21.6.15).