LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 766

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 708: UART1 RS485 Control register (RS485CTRL - address 0x4008 204C) bit description
Table 709. UART1 RS485 Address Match register (RS485ADRMATCH - address 0x4008 2050) bit description
Table 710. UART1 RS485 Delay value register (RS485DLY - address 0x4008 2054) bit description
<Document ID>
User manual
Bit
4
5
31:6
Bit
7:0
31:8
Bit
7:0
31:8
Symbol
ADRMATCH
-
Symbol
DLY
-
Symbol
DCTRL
OINV
-
33.5.19 UART1 RS-485 Address Match register
33.5.20 UART1 RS-485 Delay value register
33.5.21 RS-485/EIA-485 modes of operation
Value Description
0
1
0
1
-
Description
Contains the address match value.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
Contains the direction control (RTS or DTR) delay value. This register works in
conjunction with an 8-bit counter.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The U1RS485ADRMATCH register contains the address match value for RS-485/EIA-485
mode.
The user may program the 8-bit RS485DLY register with a delay between the last stop bit
leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of
the baud clock. Any delay time from 0 to 255 bit times may be programmed.
The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
The UART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each UART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
Direction control enable.
Disable Auto Direction Control.
Enable Auto Direction Control.
Polarity.
This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
The direction control pin will be driven to logic ‘0’ when the transmitter has data to
be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted.
The direction control pin will be driven to logic ‘1’ when the transmitter has data to
be sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 33: LPC18xx UART1
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
0
NA
Reset value
0x00
NA
Reset value
0x00
NA
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