LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 82

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LPC1837FET256,551

Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr

Specifications of LPC1837FET256,551

Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
 Details
Other names
935293795551
NXP Semiconductors
<Document ID>
User manual
9.6.7 Integer divider register B, C, D
Table 62.
Table 63.
Bit
11
23:12
28:24
31:29
Bit
0
1
5:2
10:6
11
23:12
Symbol
AUTOBLOCK
-
CLK_SEL
-
Symbol
PD
-
IDIV
-
AUTOBLOCK
-
IDIVA control register (IDIVA_CTRL, address 0x4005 0048) bit description
IDIVB/C/D control registers (IDIVB_CTRL, address 0x4005 004C; IDIVC_CTRL,
address 0x4005 0050; IDIVC_CTRL, address 0x4005 0054) bit description
…continued
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value Description
0
1
0x00
0x01
0x02
0x03
0x04
0x06
0x07
0x08
0x09
Value
0
1
0
1
Block clock automatically during frequency
change
Autoblocking disabled
Autoblocking enabled
Reserved
Clock source selection. All other values
are reserved.
32 kHz oscillator
ENET_RX_CLK
ENET_TX_CLK
GP_CLKIN
Crystal oscillator
PLL0 (for USB)
PLL0 (for audio)
PLL1
Reserved
IRC (default)
Description
Integer divider power down
IDIV enabled (default)
power-down
Reserved
Integer divider B, C, D divider values
(1/(IDIV + 1))
Reserved
Block clock automatically during frequency
change
Autoblocking disabled
Autoblocking enabled
Reserved
0000 = 1 (default)
0001 = 2
...
1111 = 16
Chapter 9: LPC18xx Clock Generation Unit (CGU)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
0x01
-
Reset
value
0
-
0000
-
0
-
Access
-
-
R/W
-
Access
R/W
-
R/W
-
R/W
R/W
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