LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 409

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.9.1.4 Set-up buffer
20.9.2 Endpoint transfer descriptor (dTD)
Table 342. Current dTD pointer
The set-up buffer is dedicated storage for the 8-byte data that follows a set-up PID.
Remark: Each endpoint has a TX and an RX dQH associated with it, and only the RX
queue head is used for receiving setup data packets.
Table 343. Set-up buffer
The dTD describes to the device controller the location and quantity of data to be
sent/received for given transfer. The DCD should not attempt to modify any field in an
active dTD except the Next Link Pointer, which should only be modified as described in
Section
Table 344. Next dTD pointer
Access
R/W
(hardware
only)
-
Dword
1
2
Access Bit
RO
20.10.11.
31:5 Next_link_pointer
4:1
0
Access
R/W
R/W
Bit
31:5
4:0
Name
-
T
All information provided in this document is subject to legal disclaimers.
Name
Current_TD_pointer Current dTD pointer
-
Bit
31:0
31:0
Rev. 00.13 — 20 July 2011
Name
BUF0
BUF1
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Description
Next link pointer
This field contains the physical memory address of the next
dTD to be processed. The field corresponds to memory
address signals [31:5], respectively.
reserved
Terminate
This bit indicates to the device controller when there are no
more valid entries in the queue.
1 - pointer is invalid
0 - Pointer is valid, i.e. pointer points to a valid transfer
element descriptor.
Description
This field is a pointer to the dTD that is represented in
the transfer overlay area. This field will be modified by
the device controller to the next dTD pointer during
endpoint priming or queue advance.
reserved
Description
Setup buffer 0
This buffer contains bytes 3 to 0 of an incoming setup
buffer packet and is written by the device controller to
be read by software.
Setup buffer 1
This buffer contains bytes 7 to 4 of an incoming setup
buffer packet and is written by the device controller to
be read by software.
UM10430
© NXP B.V. 2011. All rights reserved.
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