LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 438

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
21.4 General description
21.5 Pin description
<Document ID>
User manual
The High Speed-On-The-Go Controller is a peripheral for embedded applications
containing digital circuitry to provide USB2.0 On-The-Go functionality.
USB2.0 provides plug-and-play connection of peripheral devices to a host with three
different data speeds: High-Speed with a data rate of 480 Mbps, Full-Speed with a data
rate of 12 Mbps, Low-Speed with a data rate of 1.5 Mbps. Many portable devices can
benefit from the ability to communicate to each other over the USB interface without
intervention of a host PC. The addition of the On-The-Go functionality to USB makes this
possible without losing the benefits of the standard USB protocol.
Support of the High-Speed data rate and the OTG functionality requires an external USB
HS OTG PHY that connects to the USB controller via the ULPI interface. Full-Speed or
Low-Speed is supported through the on-chip Full-speed PHY.
Table 359. USB1 pin description
Function name
USB1_DP
USB1_DM
USB1_VBUS
USB1_VBUS_EN
USB1_IND0
USB1_IND1
USB1_PWR_FAULT
ULPI pins
ULPI_DATA[7:0]
ULPI_STP
ULPI_NXT
ULPI_DIR
ULPI_CLK
•
•
•
Supports all full-speed USB-compliant peripherals.
Supports interrupts.
This module has its own, integrated DMA engine.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Direction
I/O
I/O
I
O
O
O
I
I/O
O
I
I
I
Description
USB1 bidirectional D+ line.
USB1 bidirectional D  line.
VBUS pin (power on USB cable).
VBUS power enable.
Port indicator LED control output 0.
Port indicator LED control output 1.
Port power fault signal indicating over-current condition;
this signal monitors over-current on the USB bus (external
circuitry required to detect over-current condition).
ULPI link 8-bit bidirectional data bus timed on the rising
clock edge.
ULPI link STP signal. Asserted to end or interrupt transfers
to the PHY.
ULPI link NXT signal. Data flow control signal from the
PHY.
ULPI link DIR signal. Controls the DATA bus direction.
ULPI link CLK signal. 60 MHz clock generated by the PHY.
Chapter 21: LPC18xx USB1 Host/Device controller
UM10430
© NXP B.V. 2011. All rights reserved.
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