LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 390

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 330. USB Mode register in device mode (USBMODE_D - address 0x4000 61A8) bit description
Table 331. USB Mode register in host mode (USBMODE_H - address 0x4000 61A8) bit description
<Document ID>
User manual
Bit
4
5
31:6
Bit
1:0
2
3
Symbol Value
SDIS
-
-
Symbol Value
CM
ES
-
20.6.17.2 Host mode
0
1
-
0x0
0x1
0x2
0x3
0
1
Description
Stream disable mode
Remark: The use of this feature substantially limits the overall USB
performance that can be achieved.
Not disabled
Disabled.
Setting this bit to one disables double priming on both RX and TX for low
bandwidth systems. This mode ensures that when the RX and TX buffers
are sufficient to contain an entire packet that the standard double buffering
scheme is disabled to prevent overruns/underruns in bandwidth limited
systems. Note: In High Speed Mode, all packets received will be responded
to with a NYET handshake when stream disable is active.
Not used in device mode.
reserved
Description
Controller mode
The controller defaults to an idle state and needs to be initialized to the
desired operating mode after reset. This register can only be written once
after reset. If it is necessary to switch modes, software must reset the
controller by writing to the RESET bit in the USBCMD register before
reprogramming this register.
Idle
Reserved
Device controller
Host controller
Endian select
This bit can change the byte ordering of the transfer buffers. The bit fields in
the microprocessor interface and the DMA data structures (including the
setup buffer within the device QH) are unaffected by the value of this bit,
because they are based upon 32-bit words.
Little endian: first byte referenced in least significant byte of 32-bit word.
Big endian: first byte referenced in most significant byte of 32-bit word.
Not used in host mode
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
Reset
value
0
0
Reset
value
00
0
0
© NXP B.V. 2011. All rights reserved.
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Access
R/W
-
Access
R/ WO
R/W
-