LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1032

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 963. Pin description
<Document ID>
User manual
Symbol
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
PD_16
PE_0
PE_1
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
P11
N9
N11
T14
R13
T15
R14
P14
N14
…continued
Reset
state
[1]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
Type Description
-
I
O
-
-
-
O
-
-
-
O
-
-
I
O
-
-
-
O
-
-
-
I/O
-
-
-
I/O
-
-
-
-
I/O
-
-
-
I/O
All information provided in this document is subject to legal disclaimers.
n.c.
CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2.
EXTBUS_BLS3 — LOW active Byte Lane select signal 3.
n.c.
n.c.
n.c.
EXTBUS_CS3 — LOW active Chip Select 3 signal.
n.c.
n.c.
n.c.
EXTBUS_CS2 — LOW active Chip Select 2 signal.
n.c.
n.c.
CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.
EXTBUS_BLS2 — LOW active Byte Lane select signal 2.
n.c.
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EXTBUS_DYCS2 — SDRAM chip select 2.
n.c.
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EXTBUS_A17 — External memory address line 17.
n.c.
n.c.
n.c.
EXTBUS_A16 — External memory address line 16.
n.c.
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n.c.
n.c.
EXTBUS_A18 — External memory address line 18.
n.c.
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EXTBUS_A19 — External memory address line 19.
Rev. 00.13 — 20 July 2011
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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