LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 964

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.2.6.3 Interrupt clear enable register
Table 907. Edge configuration register (EDGE - address 0x4004 4004) bit description
Table 908. Interrupt clear enable register (CLR_EN - address 0x4004 4FD8) bit description
Bit
16
18:17 -
19
31:20 -
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
Symbol
TIM14_E
RESET_E
Symbol
WAKEUP0_CLREN Writing a 1 to this bit clears the event enable bit 0 in the
WAKEUP1_CLREN Writing a 1 to this bit clears the event enable bit 1 in the
WAKEUP2_CLREN Writing a 1 to this bit clears the event enable bit 2 in the
WAKEUP3_CLREN Writing a 1 to this bit clears the event enable bit 3 in the
ATIMER_CLREN
RTC_CLREN
BOD_CLREN
WWDT_CLREN
ETH_CLREN
USB0_CLREN
USB1_CLREN
-
CAN_CLREN
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
-
0
1
-
Rev. 00.13 — 20 July 2011
Description
ENABLE register.
ENABLE register.
ENABLE register.
ENABLE register.
Writing a 1 to this bit clears the event enable bit 4 in the
ENABLE register.
Writing a 1 to this bit clears the event enable bit 5 in the
ENABLE register.
Writing a 1 to this bit clears the event enable bit 6 in the
ENABLE register.
Writing a 1 to this bit clears the event enable bit 7 in the
ENABLE register.
Writing a 1 to this bit clears the event enable bit 8 in the
ENABLE register.
Writing a 1 to this bit clears the event enable bit 9 in the
ENABLE register.
Writing a 1 to this bit clears the event enable bit 10 in the
ENABLE register.
Reserved.
Writing a 1 to this bit clears the event enable bit 12 in the
ENABLE register.
Edge/level detect mode for combined timer output 14
event. The corresponding bit in the EDGE register must
be 0.
Level detect.
Edge detect. Detect falling edge if bit 16 in the HILO
register is 0. Detect rising edge if bit 16 in the HILO
register is 1.
Reserved.
Edge/level detect mode for RESET event. The
corresponding bit in the EDGE register must be 0.
Level detect.
Edge detect. Detect falling edge if bit 19 in the HILO
register is 0. Detect rising edge if bit 19 in the HILO
register is 1.
Reserved.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
964 of 1164
Reset
value
0
0
Reset
value
-
-
-
-
-
-
-
-
-
-
-
-
-