LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 477

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 399. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to
[1]
21.7 Functional description
<Document ID>
User manual
Bit
21
22
23
31:24 -
For control endpoints only: There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware
continuing to clear this bit. In most systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice
that the stall bit is not set after writing a one to it, software should continually write this stall bit until it is set or until a new setup has been
received by checking the associated ENDPTSETUPSTAT bit.
Symbol
TXI
TXR
TXE
0x4000 71CC (ENDPTCTRL3)) bit description
Value
0
1
0
1
-
For details on the device data structures, see
model, see
Description
Tx data toggle inhibit
This bit is only used for test and should always be written as zero.
Writing a one to this bit will cause this endpoint to ignore the data
toggle sequence and always accept data packets regardless of their
data PID.
Enabled
Disabled
Tx data toggle reset
Write 1 to reset the PID sequence.
Whenever a configuration event is received for this Endpoint,
software must write a one to this bit in order to synchronize the data
PID’s between the host and device.
Tx endpoint enable
Remark: An endpoint should be enabled only after it has been
configured
Endpoint disabled.
Endpoint enabled.
Reserved
Section
All information provided in this document is subject to legal disclaimers.
20.10.
Rev. 00.13 — 20 July 2011
…continued
Chapter 21: LPC18xx USB1 Host/Device controller
Section
20.9. For the device operational
Reset
value
0
1
0
0
UM10430
© NXP B.V. 2011. All rights reserved.
Access
R/W
WS
R/W
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