LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 655

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 568. MCPWM Count Control read address (CNTCON - 0x400A 005C) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
7
8
9
Symbol
TC0MCI0_RE
TC0MCI0_FE
TC0MCI1_RE
TC0MCI1_FE
TC0MCI2_RE
TC0MCI2_FE
TC1MCI0_RE
TC1MCI0_FE
TC1MCI1_RE
TC1MCI1_FE
26.7.10.1 MCPWM Count Control read address
26.7.10 MCPWM Count Control register
The CNTCON register controls whether the MCPWM channels are in timer or counter
mode, and in counter mode whether the counter advances on rising and/or falling edges
on any or all of the three MCI inputs. If timer mode is selected, the counter advances
based on the PCLK clock.
This address is read-only. To set or clear the register bits, write ones to the
CNTCON_SET or CNTCON_CLR address.
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Counter 0 rising edge mode, channel 0.
A rising edge on MCI0 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a rising edge on MCI0.
Counter 0 falling edge mode, channel 0.
A falling edge on MCI0 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a falling edge on MCI0.
Counter 0 rising edge mode, channel 1.
A rising edge on MCI1 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a rising edge on MCI1.
Counter 0 falling edge mode, channel 1.
A falling edge on MCI1 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a falling edge on MCI1.
Counter 0 rising edge mode, channel 2.
A rising edge on MCI0 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a rising edge on MCI2.
Counter 0 falling edge mode, channel 2.
A falling edge on MCI0 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a falling edge on MCI2.
Counter 1 rising edge mode, channel 0.
A rising edge on MCI0 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a rising edge on MCI0.
Counter 1 falling edge mode, channel 0.
A falling edge on MCI0 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a falling edge on MCI0.
Counter 1 rising edge mode, channel 1.
A rising edge on MCI1 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a rising edge on MCI1.
Counter 1 falling edge mode, channel 1.
A falling edge on MCI0 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a falling edge on MCI1.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
0
0
0
0