LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 546

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 455. Register overview: LCD controller (base address: 0x4000 8000)
[1]
<Document ID>
User manual
Name
CRSR_INTCLR
CRSR_INTRAW
CRSR_INTSTAT
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
23.6.1 Horizontal Timing register
Access Address offset
WO
RO
RO
The TIMH register controls the Horizontal Synchronization pulse Width (HSW), the
Horizontal Front Porch (HFP) period, the Horizontal Back Porch (HBP) period, and the
Pixels-Per-Line (PPL).
Table 456. Horizontal Timing register (TIMH, address 0x4000 8000) bit description
Bits
1:0
7:2
15:8
23:16
31:24
0xC24
0xC28
0xC2C
Symbol
-
PPL
HSW
HFP
HBP
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Pixels-per-line.
The PPL bit field specifies the number of pixels in each line or
row of the screen. PPL is a 6-bit value that represents between
16 and 1024 pixels per line. PPL counts the number of pixel
clocks that occur before the HFP is applied.
Program the value required divided by 16, minus 1. Actual
pixels-per-line = 16 * (PPL + 1). For example, to obtain 320
pixels per line, program PPL as (320/16) -1 = 19.
Horizontal synchronization pulse width.
The 8-bit HSW field specifies the pulse width of the line clock in
passive mode, or the horizontal synchronization pulse in active
mode. Program with desired value minus 1.
Horizontal front porch.
The 8-bit HFP field sets the number of pixel clock intervals at the
end of each line or row of pixels, before the LCD line clock is
pulsed. When a complete line of pixels is transmitted to the LCD
driver, the value in HFP counts the number of pixel clocks to wait
before asserting the line clock. HFP can generate a period of
1-256 pixel clock cycles. Program with desired value minus 1.
Horizontal back porch.
The 8-bit HBP field is used to specify the number of pixel clock
periods inserted at the beginning of each line or row of pixels.
After the line clock for the previous line has been deasserted, the
value in HBP counts the number of pixel clocks to wait before
starting the next display line. HBP can generate a delay of 1-256
pixel clock cycles. Program with desired value minus 1.
Description
Cursor Interrupt Clear register
Cursor Raw Interrupt Status register
Cursor Masked Interrupt Status register
…continued
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
-
0x0
0x0
0x0
0x0
Reset
value
[1]
0x0
0x0
0x0