LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 386

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 327. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 6184) bit description
<Document ID>
User manual
Bit
22
23
24
25
27:26 PSPD
31:28 -
Symbol
WKOC
PHCD
PFSC
-
20.6.16 OTG Status and Control register (OTGSC)
Value Description
0
1
0
1
0
1
-
0x0
0x1
0x2
Table 328. Port states as described by the PE and SUSP bits in the PORTSC1 register
The OTG register has four sections:
PE bit
0
1
1
•
•
•
•
PHY low power suspend - clock disable (PLPSCD)
Port force full speed connect
Reserved
Port speed
Full-speed
Low-speed
Reserved
Wake on over-current enable (WKOC_E)
Disables the port to wake up on over-current events.
Writing a one to this bit enabled the port to be sensitive to over-current
conditions as wake-up events.
In host mode, the PHY can be put into Low Power Suspend – Clock
Disable when the downstream device has been put into suspend mode or
when no downstream device is connected. Low power suspend is
completely under the control of software.
Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the
PHY clock (enabled).
Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the
PHY clock (disabled).
Port connects at any speed.
Writing this bit to a 1 will force the port to only connect at Full Speed. It
disables the chirp sequence that allows the port to identify itself as High
Speed. This is useful for testing FS configurations with a HS host, hub or
device.
This register field indicates the speed at which the port is operating. For HS
mode operation in the host controller and HS/FS operation in the device
controller the port routing steers data to the Protocol engine. For FS and
LS mode operation in the host controller, the port routing steers data to the
Protocol Engine w/ Embedded Transaction Translator.
High-speed
OTG interrupt enables (R/W)
OTG Interrupt status (R/WC)
OTG status inputs (RO)
OTG controls (R/W)
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
SUSP bit
0 or 1
0
1
Port state
disabled
enabled
suspend
UM10430
0
0
Reset
value
0
0
-
© NXP B.V. 2011. All rights reserved.
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R/W
R/W
Access
R/W
RO
-