LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 309

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
18.6.13 Response Register 0 (RESP0)
18.6.14 Response Register 1 (RESP1)
18.6.15 Response Register 2 (RESP2)
18.6.16 Response Register 3 (RESP3)
18.6.17 Masked Interrupt Status Register (MINTSTS)
Table 237. Response Register 0 (RESP0, address 0x4000 4030) bit description
Table 238. Response Register 1 (RESP1, address 0x4000 4034) bit description
Table 239. Response Register 2 (RESP2, address 0x4000 4038) bit description
Table 240. Response Register 3 (RESP3, address 0x4000 403C) bit description
Table 241. Masked Interrupt Status Register (MINTSTS, address 0x4000 4040) bit description
Bit
31:0
Bit
31:0
Bit
31:0
Bit
31:0
Bit
0
1
2
3
4
Symbol
RESPONSE1
Symbol
CD
RE
CD
DTO
TXDR
Symbol
RESPONSE0
Symbol
RESPONSE2
Symbol
RESPONSE3
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Card detect. Interrupt enabled only if corresponding bit in
interrupt mask register is set.
Response error. Interrupt enabled only if corresponding bit
in interrupt mask register is set.
Command done. Interrupt enabled only if corresponding bit
in interrupt mask register is set.
Data transfer over. Interrupt enabled only if corresponding
bit in interrupt mask register is set.
Transmit FIFO data request. Interrupt enabled only if
corresponding bit in interrupt mask register is set.
Description
Register represents bit[63:32] of long response. When CIU
sends auto-stop command, then response is saved in
register. Response for previous command sent by host is
still preserved in Response 0 register. Additional auto-stop
issued only for data transfer commands, and response type
is always short for them. For information on when CIU
sends auto-stop commands, refer to Auto-Stop <tbd>.
Description
Bit[31:0] of response
Description
Bit[95:64] of long response
Description
Bit[127:96] of long response
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
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