LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 75

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
9.6.3.1 PLL0 (for USB) status register
9.6.3.2 PLL0 (for USB) control register
9.6.3 PLL0 (for USB) registers
Table 50.
The PLL0 provides a dedicated clock to the High-speed USB0 interface and to USB1.
See
Table 51.
Table 52.
Bit
1
2
31:3
Bit
0
1
31:2
Bit
0
1
2
Section 9.7.4.5
Symbol
BYPASS
HF
-
Symbol
PD
BYPASS
DIRECTI
Symbol
LOCK
FR
-
XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bit
description
PLL0USB status register (PLL0USB_STAT, address 0x4005 001C) bit description
PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
for instructions on how to set up the PLL0.
Rev. 00.13 — 20 July 2011
Description
PLL0 lock indicator
PLL0 free running indicator
Reserved
Value
0
1
0
1
Configure crystal operation or external-clock input
pin XTAL1. Do not change the BYPASS and
ENABLE bits in one write-action: this will result in
unstable device operation!
Operation with crystal connected (default).
Bypass mode. Use this mode when an external
clock source is used instead of a crystal.
Select frequency range
Oscillator low-frequency mode (crystal or external
clock source 1 to 20 MHz). Between 15 MHz to 20
MHz, the state of the HF bit is don’t care.
Oscillator high-frequency mode; crystal or external
clock source 15 to 25 MHz. Between 15 MHz to 20
MHz, the state of the HF bit is don’t care (default)
Reserved
Description
PLL0 power down
PLL0 enabled
PLL0 powered down
Input clock bypass control
CCO clock sent to post-dividers. Use this
in normal operation.
PLL0 input clock sent to post-dividers
(default).
PLL0 direct input
Chapter 9: LPC18xx Clock Generation Unit (CGU)
UM10430
Reset
value
0
0
© NXP B.V. 2011. All rights reserved.
0
Reset
value
1
1
Reset
value
0
1
-
R
-
Access
R
Access
R/W
R/W
-
Access
R/W
R/W
R/W
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