LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 448

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 370. USB Status register in device mode (USBSTS_D - address 0x4000 7144) register bit description
<Document ID>
User manual
Bit
7
8
11:9
12
13
14
15
16
17
18
19
31:20
Symbol
SRI
SLI
-
-
-
-
-
NAKI
-
-
-
-
Value
0
1
0
1
-
-
-
-
-
0
1
-
-
All information provided in this document is subject to legal disclaimers.
Description
SOF received
This bit is cleared by software writing a one to it.
When the device controller detects a Start Of
(micro) Frame, this bit will be set to a one. When
a SOF is extremely late, the device controller will
automatically set this bit to indicate that an SOF
was expected. Therefore, this bit will be set
roughly every 1 ms in device FS mode and every
125  s in HS mode and will be synchronized to
the actual SOF that is received. Since the device
controller is initialized to FS before connect, this
bit will be set at an interval of 1ms during the
prelude to connect and chirp.
DCSuspend
The device controller clears the bit upon exiting
from a suspend state. This bit is cleared by
software writing a one to it.
When a device controller enters a suspend state
from an active state, this bit will be set to a one.
Reserved. Software should only write 0 to
reserved bits.
Not used in Device mode.
Not used in Device mode.
Not used in Device mode.
Not used in Device mode.
NAK interrupt bit
This bit is automatically cleared by hardware
when the all the enabled TX/RX Endpoint NAK
bits are cleared.
It is set by hardware when for a particular
endpoint both the TX/RX Endpoint NAK bit and
the corresponding TX/RX Endpoint NAK Enable
bit are set.
Reserved. Software should only write 0 to
reserved bits.
Not used in Device mode.
Not used in Device mode.
Reserved. Software should only write 0 to
reserved bits.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
Reset
value
0
0
0
0
0
0
0
0
0
0
0
UM10430
© NXP B.V. 2011. All rights reserved.
Access
R/WC
R/WC
RO
-
-
-
-
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