LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 860

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
37.7.5.1 Selecting the appropriate I
37.7.4 I
37.7.5 I
Table 804. I
This register is readable and writable and are only used when an I
slave mode. In master mode, this register has no effect. The LSB of ADR is the General
Call bit. When this bit is set, the General Call address (0x00) is recognized.
If this register contains 0x00, the I
register will be cleared to this disabled state on reset. See also
Table 805. I
Table 806. I
Table 807. I
Software must set values for the registers SCLH and SCLL to select the appropriate data
rate and duty cycle. SCLH defines the number of C_PCLK cycles for the SCL HIGH time,
SCLL defines the number of I2C_PCLK cycles for the SCL low time. The frequency is
determined by the following formula (I2C_PCLK is the frequency of the peripheral I2C
clock):
Bit
7:0
31:8 -
Bit
0
7:1
31:8 -
Bit
15:0
31:16
Bit
15:0
31:16
2
2
C Slave Address register 0
C SCL HIGH and LOW duty cycle registers
Symbol
Data
Symbol
GC
Address
Symbol
SCLH
-
Symbol
SCLL
-
description
0x400E 000C (I2C1)) bit description
0x400E 0010 (I2C1)) bit description
0x400E 0014 (I2C1)) bit description
2
2
2
2
C Data register (DAT - 0x400A 1008 (I2C0) and 0x400E 0008 (I2C1)) bit
C Slave Address register 0 (ADR0 - address 0x400A 100C (I2C0) and
C SCL HIGH Duty Cycle register (SCLH - address 0x400A 1010 (I2C0) and
C SCL Low duty cycle register (SCLL - address 0x400A 1014 (I2C0) and
All information provided in this document is subject to legal disclaimers.
Description
This register holds data values that have been received or are
to be transmitted.
Reserved. The value read from a reserved bit is not defined.
Description
General Call enable bit.
The I
Reserved. The value read from a reserved bit is not defined.
Description
Count for SCL HIGH time period selection.
Reserved. The value read from a reserved bit is not defined.
Description
Count for SCL low time period selection.
Reserved. The value read from a reserved bit is not defined.
2
Rev. 00.13 — 20 July 2011
C device address for slave mode.
2
C data rate and duty cycle
2
C will not acknowledge any address on the bus. This
Chapter 37: LPC18xx I2C-bus interface
Table
2
C interface is set to
811.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
-
-
Reset value
0
0x00
Reset value
0x0004
-
Reset value
0x0004
-
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