LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1053

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.7.4.12 EMC data in delay register
Table 976. EMC address delay register 2 (EMCADDRDELAY2, address 0x4008 6D1C) bit
This register provides a programmable delay for the EMC data inputs (8 data lanes per
delay control). The delay for each control output is approximately 0.5 ns 
ADDRn_DELAY. (ADDRn_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay
 3.5 ns.)
Table 977. EMC data in delay register 3 (EMCDINDELAY, address 0x4008 6D24) bit
Bit
2:0
3
6:4
7
10:8
11
14:12
15
18:16
19
22:20
23
26:24
27
30:28
31
Bit
2:0
3
6:4
7
10:8
11
14:12
15
18:16
19
22:20
23
26:24
31:27
Symbol
ADDR16_DELAY Delay of the EXTBUS_A16 output.
-
ADDR17_DELAY Delay of the EXTBUS_A17 output.
-
ADDR18_DELAY Delay of the EXTBUS_A18 output.
-
ADDR19_DELAY Delay of the EXTBUS_A19 output.
-
ADDR20_DELAY Delay of the EXTBUS_A20 output.
-
ADDR21_DELAY Delay of the EXTBUS_A21 output.
-
ADDR22_DELAY Delay of the EXTBUS_A22 output.
-
ADDR23_DELAY Delay of the EXTBUS_A23 output.
-
Symbol
DIN0_DELAY
-
DIN1_DELAY
-
DIN2_DELAY
-
DIN3_DELAY
-
DEN0_DELAY
-
DEN1_DELAY
-
DEN2_DELAY
-
description
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Description
Delay of the EXTBUS_D0 to EXTBUS_D7 inputs.
Reserved.
Delay of the EXTBUS_D8 to EXTBUS_D15 inputs.
Reserved.
Delay of the EXTBUS_D23 to EXTBUS_D16 inputs. 0
Reserved.
Delay of the EXTBUS_D31 to EXTBUS_D24 inputs. 0
Reserved.
Delay of the data enable lines 0 to 7.
Reserved.
Delay of the data enable lines 8 to 15.
Reserved.
Delay of the data enable lines 16 to 23.
Reserved.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
Reset
value
0
-
0
-
-
-
0
-
0
-
0
-
1053 of 1164
Access
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Access
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-