LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 640

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 549. MCPWM Control read address (CON - 0x400A 0000) bit description
<Document ID>
User manual
Bit
10
11
12
15:13
16
17
18
19
20
28:21
29
30
Symbol
POLA1
DTE1
DISUP1
-
RUN2
CENTER2
POLA2
DTE2
DISUP2
-
INVBDC
ACMODE
Value Description
0
1
0
1
0
1
-
0
1
0
1
0
1
0
1
0
1
-
0
1
0
1
Selects polarity of the MCOA1 and MCOB1 pins.
Passive state is LOW, active state is HIGH.
Passive state is HIGH, active state is LOW.
Controls the dead-time feature for channel 1.
Dead-time disabled.
Dead-time enabled.
Enable/disable updates of functional registers for channel 1 (see
Functional registers are updated from the write registers at the end of each PWM
cycle.
Functional registers remain the same as long as the timer is running.
Reserved.
Stops/starts timer channel 2.
Stop.
Run.
Edge/center aligned operation for channel 2.
Edge-aligned.
Center-aligned.
Selects polarity of the MCOA2 and MCOB2 pins.
Passive state is LOW, active state is HIGH.
Passive state is HIGH, active state is LOW.
Controls the dead-time feature for channel 1.
Dead-time disabled.
Dead-time enabled.
Enable/disable updates of functional registers for channel 2 (see
Functional registers are updated from the write registers at the end of each PWM
cycle.
Functional registers remain the same as long as the timer is running.
Reserved.
Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set
to 1 only in 3-phase DC mode.
The MCOB outputs have opposite polarity from the MCOA outputs (aside from
dead time).
The MCOB outputs have the same basic polarity as the MCOA outputs. (see
Section
3-phase AC mode select (see
3-phase AC-mode off: Each PWM channel uses its own timer-counter and period
register.
3-phase AC-mode on: All PWM channels use the timer-counter and period register
of channel 0.
26.8.6)
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
Section
26.8.7).
Section
Section
UM10430
© NXP B.V. 2011. All rights reserved.
26.8.2).
26.8.2).
640 of 1164
0
0
0
0
0
Reset
value
0
0
0
0
0