LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 971
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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Table 915. Register overview: Configuration registers (base address 0x4004 3000)
<Document ID>
User manual
Name
IRCTRM
CREG0
PMUCON
-
M3MEMMAP
-
CREG1
CREG2
CREG3
CREG4
CREG5
DMAMUX
-
ETBCFG
CREG6
-
CHIPID
-
-
-
-
-
LOCKREG
42.3.4.1 IRC trim register
42.3.4 Register description
Access
RO
R/W
-
R/W
-
RO
RO
RO
RO
R/W
R/W
-
R/W
R/W
-
RO
-
-
-
-
-
Table 916. IRC trim register (IRCTRM, address 0x4004 3000) bit description
Bit
11:0
19:12
31:20
Address
offset
0x000
0x004
0x008
0x008 -
0x0FC
0x100
0x104
0x108
0x10C
0x110
0x114
0x118
0x11C
0x120 -
0x124
0x128
0x12C
0x130 -
0x1FC
0x200
0x204 -
0x2FC
0x300
0x304
0x308
0x30C -
0xEFC
0xF00
Symbol
TRM
-
-
Description
IRC trim register
Chip configuration register 32 kHz oscillator output and BOD
control register.
Power mode control register.
Reserved
ARM Cortex-M3 memory mapping
Reserved
Chip configuration register 1
Chip configuration register 2
Chip configuration register 3
Chip configuration register 4
Chip configuration register 5. Controls JTAG access.
DMA muxing control
Reserved
ETB RAM configuration
Chip configuration register 6.
Reserved
Part ID
Reserved
Reserved
Reserved
Reserved
Reserved
Lock register; blocks write access to CREG registers
All information provided in this document is subject to legal disclaimers.
Description
IRC trim value
Reserved
Reserved
Rev. 00.13 — 20 July 2011
Chapter 42: Appendix
UM10430
Reset
value
0x2BC
0xFF
-
© NXP B.V. 2011. All rights reserved.
Reset value
0x000F F2BC
0x0000 0000
-
-
-
0x0000 0000
-
-
-
Access
R
R
-
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