LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 113

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 89.
The RGU also monitors the reset cause for each reset output. The reset cause can be
retrieved with two levels of granularity.
The first level is monitored by the RESET_STATUS0 to 3 registers and indicates one of
the following reset causes (see
The second level of granularity is monitored by one individual register for each reset
output (RESET_EXT_STATUSn) in which the detailed reset cause is indicated, that is
whether or not any of the possible inputs to each reset generator are activated. The
following lists all inputs, but note that only a subset of inputs are connected to each reset
generator:
Reset output
generator
ADC0_RST
ADC1_RST
DAC_RST
Reserved
UART0_RST
UART1_RST
UART2_RST
UART3_RST
I2C0_RST
I2C1_RST
SSP0_RST
SSP1_RST
I2S_RST
SPIFI_RST
CAN1_RST
CAN0_RST
Reserved
Reserved
Reserved
•
•
•
•
•
•
•
No reset has taken place.
Reset generated by software (using the registers RESET_CTRL0 and
RESET_CTRL1).
Reset generated by any of the reset sources.
External reset (from external reset pin)
CORE_RST output
PERIPH_RST output
MASTER_RST output
Reset output configuration
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Reset
output
#
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
59 - 63
Table 94
Reset source
PERIPH_RST
PERIPH_RST
PERIPH_RST
-
PERIPH_RST
PERIPH_RST
PERIPH_RST
PERIPH_RST
PERIPH_RST
PERIPH_RST
PERIPH_RST
PERIPH_RST
PERIPH_RST
PERIPH_RST
PERIPH_RST
PERIPH_RST
-
-
-
Chapter 11: LPC18xx Reset Generation Unit (RGU)
…continued
to
Table
97):
Parts of the device reset when
activated
ADC0 reset (ADC register interface and
analog block)
ADC1 reset (ADC register interface and
analog block)
DAC reset (DAC register interface and
analog block)
-
USART0 reset
UART1 reset
USART2 reset
USART3 reset
I2C0 reset
I2C1 reset
SSP0 reset
SSP1 reset
I2S0 and I2S1 reset
SPIFI reset
C_CAN1 reset
C_CAN0 reset
-
-
-
UM10430
© NXP B.V. 2011. All rights reserved.
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