LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 6

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
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User manual
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– Two I
Digital peripherals:
– External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
– LCD controller with DMA support and a programmable display resolution of up to
– SD/MMC card interface.
– Eight-channel General-Purpose DMA (GPDMA) controller can access all
– Up to 80 General-Purpose Input/Output (GPIO) pins with configurable
– GPIO registers are located on the AHB for fast access. GPIO ports have DMA
– State Configurable Timer (SCT) subsystem on AHB.
– Four general-purpose timer/counters with capture and match capabilities.
– One motor control PWM for three-phase motor control.
– One Quadrature Encoder Interface (QEI).
– Repetitive Interrupt timer (RI timer).
– Windowed watchdog timer.
– Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
– Alarm timer; can be battery powered.
Digital peripherals available on flash-based parts LPC18xx only:
– <tbd>
Analog peripherals:
– One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
– Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
Security:
– Hardware-based AES security engine programmable through an on-chip API.
– Two 128-bit secure OTP memories for AES key storage and customer use.
– Unique ID for each device.
Power:
– Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator
– RTC power domain can be powered separately by a 3 V battery supply.
– Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
– Processor wake-up from Sleep mode via wake-up interrupts from various
and SDRAM devices.
1024H  768V. Supports monochrome and color STN panels and TFT color
panels; supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping.
memories on the AHB and all DMA-capable AHB slaves.
pull-up/pull-down resistors and open-drain modes.
support.
of battery powered backup registers.
for the core supply and the RTC power domain.
power-down.
peripherals.
2
S interfaces with DMA support, each with one input and one output.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 1: Introductory information
UM10430
© NXP B.V. 2011. All rights reserved.
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