LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 598

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.6.8 SCT state register
24.6.9 SCT input register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
STATE_L (address 0x4000 4044) and STATE_H (address 0x4000 4046). Both the L and
H registers can be read or written in a single 32-bit read or write operation, or they can be
read or written individually.
Software can read the state associated with a counter at any time. Writing the state is only
allowed when the counter’s HALT bit is 1; when HALT is 0, a write attempt does not
change the state and results in a bus error.
The state variable is the main feature that distinguishes the SCT from other counter/timer/
PWM blocks. Events can be made to occur only in certain states. Events, in turn, can
perform the following actions:
The value of a state variable is completely under the control of the application. If an
application does not use states, the value of the state variable remains zero, which is the
default value.
A state variable can be used to track and control multiple cycles of the associated counter
in any desired operational sequence, and it is logically associated with a state machine
diagram which represents the SCT configuration. See
more about the relationship between states and events.
All possible values for the state variable are set by the STATELD/STADEV fields in the
event control registers of all defined events. The change of the state variable during
multiple counter cycles reflects how the associated state machine moves from one state
to the next.
Table 507. SCT state register (STATE - address 0x4000 0044) bit description
Software can read the state of the SCT’s inputs in this read-only register in two slightly
different forms. The only situation in which these will differ is if CLKMODE = 2 in the
CONFIG register.
Bit
4:0
15:5
20:16
31:21
•
•
•
•
set and clear outputs
limit, stop, and start the counter
cause interrupts and DMA requests
modify the state variable
Symbol
STATE_L
-
STATE_H
-
All information provided in this document is subject to legal disclaimers.
Description
State variable.
Reserved.
State variable.
Reserved.
Rev. 00.13 — 20 July 2011
Chapter 24: LPC18xx State Configurable Timer (SCT)
Section 24.6.23
UM10430
and
© NXP B.V. 2011. All rights reserved.
24.6.24
598 of 1164
Reset
value
0
-
0
for