LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 33

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

4.1 How to read this chapter
4.2 Features
4.3 General description
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User manual
All LPC18xx parts support AES decoding.
The LPC18xx uses an external image to store instruction code and data. If customers
want to protect the external image content, then the LPC18xx offers hardware to
accelerate processing for data decoding, data integrity and proof of origin.
The hardware consists of:
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UM10430
Chapter 4: LPC18xx Security features
Rev. 00.13 — 20 July 2011
Decoding of external image data.
Secure storage of decoding keys.
Support for CMAC hash calculation to authenticate data.
AES engine performance of 1 byte/clock cycle.
AES engine supports:
– ECB decode mode with 128-bit key.
– CBC decode mode with 128-bit key.
– CMAC hash calculation.
One-time programmable (OTP) non-volatile memories to store the AES key. Two
instances (OTP1/2) are offered to store two keys. A 3rd OTP (OTP3) is used by the
LPC18xx for storing other data.
An AES engine to perform the AES decoding. This engine supports an external
GPDMA module to read and write data. The engine uses a 128-bit key and processes
blocks of 128-bit. The key can use a dedicated hardware interface that is not visible to
software or a software interface.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
User manual
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