LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 289

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
16.8.2.3 Memory-to-memory DMA flow
For a memory-to-memory DMA flow the following sequence occurs:
Note: Memory-to-memory transfers should be programmed with a low channel priority,
otherwise other DMA channels cannot access the bus until the memory-to-memory
transfer has finished, or other AHB masters cannot perform any transaction.
4. If an error occurs while transferring the data an error interrupt is generated, the DMA
5. Decrement the transfer count if the DMA Controller is performing the flow control.
6. If the transfer has completed (indicated by the transfer count reaching 0 if the DMA
7. When the destination DMA request goes active and there is data in the DMA
8. If an error occurs while transferring the data, an error interrupt is generated, the DMA
9. If the transfer has completed it is indicated by the transfer count reaching 0 if the DMA
1. Program and enable the DMA channel.
2. Transfer data whenever the DMA channel has the highest pending priority and the
3. If an error occurs while transferring the data, generate an error interrupt and disable
4. Decrement the transfer count.
5. If the count has reached zero:
– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The DMA Controller is the bus master of the AHB bus.
stream is disabled, and the flow sequence ends.
Controller is performing flow control, or by the peripheral sending a DMA request if the
peripheral is performing flow control):
– The DMA Controller responds with a DMA acknowledge to the source peripheral.
– Further source DMA requests are ignored.
Controller FIFO, transfer data into the destination peripheral.
stream is disabled, and the flow sequence ends.
Controller is performing flow control, or by the sending a DMA request if the peripheral
is performing flow control. The following happens:
– The DMA Controller responds with a DMA acknowledge to the destination
– The terminal count interrupt is generated (this interrupt can be masked).
– If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI,
DMA Controller gains mastership of the AHB bus.
the DMA stream.
– Generate a terminal count interrupt (the interrupt can be masked).
– If the CLLI Register is not 0, then reload the CSRCADDR, CDESTADDR, CLLI,
peripheral.
and CCONTROL Registers and go to back to step 2. However, if CLLI is 0, the
DMA stream is disabled and the flow sequence ends.
and CCONTROL Registers and go to back to step 2. However, if CLLI is 0, the
DMA stream is disabled and the flow sequence ends.
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
UM10430
© NXP B.V. 2011. All rights reserved.
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