LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 614

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.7.8 DMA operation
24.7.9 Alternate addressing for match/capture registers
A DMA controller can be used to write one or more Reload registers, or read one or more
Capture registers, typically at the start of a counter cycle. DMA access to more than one
Reload or Capture register requires that they be consecutive registers. (Nothing else in
the SCT constrains how these registers are assigned and used.)
A DMA request can be set by an event or when a counter’s Match registers are loaded
from its Reload registers, as described in
used to do the same kind of register access for both counters when UNIFY is 0, or one
request can be used for writing Reload registers and the other for reading Capture
registers.
The SCT does not know how many transfers should be done for each request, so it
cannot control its DMA requests accordingly.
The two DMA requests are connected to DMABREQ7 and DMABREQ8. The number of
registers to be transferred for each request should be written to the TransferSize field in
the Channel Control Register of the DMA channel to which the request is connected. If the
Linked List feature is used, there is a TransferSize value in each Linked List entry. The
GPDMA asserts the DMACCLR signal when that number of transfers has been
completed, which makes the SCT clear the request.
The Match, Reload, Capture, and Capture Control registers are arranged as consecutive
words, with the standard division of each word into two halfwords. When the UNIFY bit is
zero, these two halfwords are related to the L and H counters. Software has the option of
writing words initially to set up both halves of a SCT simultaneously, or writing halfwords to
set up each half separately.
Applications can use a DMA controller to write Reload registers or to read Capture
registers. However, when UNIFY is 0, the addressing of the halfword registers is not
compatible with many DMA controllers’ requirement to use consecutive addresses for
sequential-address operation.
occupied by each type of register contains an alternate address map for halfword
accesses to the same registers, which is compatible with such DMA controllers. When
UNIFY is 1, DMA word accesses should be done using standard offsets.
Table 528. Alternate address map for DMA halfword access
Match register
MATCH0_L
MATCH0_H
MATCH1_L
MATCH1_H
...
MATCHREL0_L
MATCHREL0_H
MATCHREL1_L
MATCHREL1_H
...
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Capture register
CAP0_L
CAP0_H
CAP1_L
CAP1_H
...
CAPCTRL0_L
CAPCTRL0_H
CAPCTRL1_L
CAPCTRL1_H
...
Table 528
Chapter 24: LPC18xx State Configurable Timer (SCT)
shows how the second half of the range
Section
Standard offset
0x100
0x102
0x104
0x106
...
0x200
0x202
0x204
0x206
...
24.6.14. The SCT’s two requests can be
DMA halfword offset
0x180
0x1C0
0x182
0x1C2
...
0x280
0x2C0
0x282
0x2C2
...
UM10430
© NXP B.V. 2011. All rights reserved.
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