LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 257

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
15.5.2.3 GPIO grouped interrupt port enable registers
15.5.3.1 GPIO port byte pin registers
15.5.3 GPIO port register description
Table 182. GPIO grouped interrupt port polarity registers (PORT_POL, addresses 0x4008
The grouped interrupt port enable registers enable the pins which contribute to the
grouped interrupt. Each port n (n = 0 to 7) is associated with its own port enable register,
and the values of all registers together determine which pins contribute to the grouped
interrupt.
Table 183. GPIO grouped interrupt port n enable registers (PORT_ENA, addresses 0x4008
Each GPIO pin GPIOn[m] has a byte register in this address range. The byte pin registers
of GPIO port 0 correspond to registers B0 to B31, the byte pin registers of GPIO port 1
correspond to registers B32 to B63, etc.. Byte addresses are reserved for unused GPIO
port pins (see
Software typically reads and writes bytes to access individual pins but also can read or
write halfwords to sense or set the state of two pins, and read or write words to sense or
set the state of four pins.
Table 184. GPIO port byte pin registers (B, addresses 0x400F 4000 (B0) to 0x400F 00FC
Bit
31:0
Bit
31:0
Bit
0
7:1
Symbol Description
POL
Symbol Description
ENA
Symbol Description
PBYTE Read: state of the pin GPIOn[m], regardless of direction,
8020 (PORT_POL0) to 0x4008 803C (PORT_POL7) (GROUP0 INT) and 0x4008 9020
(PORT_POL0) to 0x4008 903C (PORT_POL7) (GROUP1 INT)) bit description
8040 (PORT_ENA0) to 0x4008 805C (PORT_ENA7) (GROUP0 INT) and 0x4008 9040
(PORT_ENA0) to 0x4008 905C (PORT_ENA7) (GROUP1 INT)) bit description
(B255)) bit description
Table
All information provided in this document is subject to legal disclaimers.
Configure pin polarity of port n pins for group interrupt. Bit m
corresponds to pin GPIOn[m] of port n.
0 = the pin is active LOW. If the level on this pin is LOW, the
pin contributes to the group interrupt.
1 = the pin is active HIGH. If the level on this pin is HIGH, the
pin contributes to the group interrupt.
Enable port n pin for group interrupt. Bit m corresponds to pin
GPIOPn[m] of port n.
0 = the port n pin is disabled and does not contribute to the
grouped interrupt.
1 = the port n pin is enabled and contributes to the grouped
interrupt.
masking, or alternate function. Pins configured as analog I/O
always read as 0.
Write: loads the pin’s output bit.
Reserved (0 on read, ignored on write)
165).
Rev. 00.13 — 20 July 2011
Chapter 15: LPC18xx GPIO
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
1
Reset
value
0
Reset
value
ext
0
257 of 1164
Access
-
Access
-
Access
R/W
-