LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 96

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
9.7.6.5 Selectable feedback divider clock
9.7.6.6 Direct output mode
9.7.6.7 Divider ratio programming
9.7.6.8 Frequency selection
the PLL is not in lock. When the Power-down mode is terminated, the PLL will resume its
normal operation and will make the lock signal high once it has regained lock on the input
clock.
To allow a trade-off to be made between functionality and power consumption, the
feedback divider can be connected to either the CCO clock by setting FBSEL to 0 or to the
output clock by setting FBSEL to 1. If the post-divider is used to divide down the CCO
clock the current consumption of the feedback divider can be reduced by making it run on
the lower output clock instead of the CCO clock, but doing so will limit the relation
between output and phase detector clock frequencies to integer values.
In normal operating mode (with DIRECT set to 0) the CCO clock is divided by 2, 4, 8 or 16
depending on the value of PSEL[1:0], automatically giving an output clock with a 50%
duty cycle. If a higher output frequency is needed, the CCO clock can be sent directly to
the output by setting DIRECT to 1. Since the CCO was designed to directly generate a
clock with a 50% duty cycle, the output clock duty cycle will also be 50% in direct mode.
Pre-divider
The pre-divider’s division ratio is controlled by the NSEL[1:0] input. The division ratio
between PLL’s input clock and the phase detector clock is the decimal value on NSEL[1:0]
plus one.
Post-divider
The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two
times the value of P selected by PSEL bits. This guarantees an output clock with a 50%
duty cycle.
Feedback divider
The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio
between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus
one.
Changing the divider values
Changing the divider ratio while the PLL is running is not recommended. As there is no
way to synchronize the change of the NSEL, MSEL, and PSEL values with the dividers,
the risk exists that the counter will read in an undefined value, which could lead to
unwanted spikes or drops in the frequency of the output clock. The recommended way of
changing between divider settings is to power down the PLL, adjust the divider settings
and then let the PLL start up again.
The PLL frequency equations use the following parameters (also see
Integer mode
In this mode the post divider is enabled and the feedback divider is set to run on the PLL
output clock, giving the following frequency relations:
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 9: LPC18xx Clock Generation Unit (CGU)
Figure
UM10430
© NXP B.V. 2011. All rights reserved.
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