LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 526

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.8.2.8 Receive process suspended
22.8.2.9 Interrupts
If a new Receive frame arrives while the Receive Process is in Suspend state, the DMA
refetches the current descriptor in the Host memory. If the descriptor is now owned by the
DMA, the Receive Process re-enters the Run state and starts frame reception. If the
descriptor is still owned by the host, by default, the DMA discards the current frame at the
top of the MTL Rx FIFO and increments the missed frame counter. If more than one frame
is stored in the MTL Rx FIFO, the process repeats.
The discarding or flushing of the frame at the top of the MTL Rx FIFO can be avoided by
setting Operation Mode register bit 24 (DFF) in
process sets the Receive Buffer Unavailable status and returns to the Suspend state.
Interrupts can be generated as a result of various events. The DMA Status register
(Table
enable bit for each of the events that can cause an interrupt.
There are two groups of interrupts, Normal and Abnormal, as described in DMA Status
register
When all the enabled interrupts within a group are cleared, the corresponding summary
bit is cleared. When both the summary bits are cleared, the interrupt signal is de-asserted.
If the MAC core is the cause for assertion of the interrupt, then any of the GLI, GMI, or GPI
bits of DMA Status register
Remark: The DMA Status register
interrupt pin is asserted because of any event in this status register only if the
corresponding interrupt enable bit is set in DMA Interrupt Enable Register
Interrupts are not queued and if the interrupt event occurs before the driver has
responded to it, no additional interrupts are generated. For example, the Receive Interrupt
(bit 6 of the DMA Status Register
transferred to the Host buffer. The driver must scan all descriptors, from the last recorded
position to the first one owned by the DMA.
An interrupt is generated only once for simultaneous, multiple events. The driver must
scan the DMA Status register
generated again unless a new interrupting event occurs, after the driver has cleared the
appropriate bit in DMA Status register. For example, the controller generates a DMA
Receive interrupt (bit 6 of the DMA Status register), and the driver begins reading DMA
Status register . Next, Receive Buffer Unavailable (bit 7 of DMA Status register (Status
Register)) occurs. The driver clears the Receive interrupt. Even then, the sbd_intr_o
signal is not de-asserted, because of the active or pending Receive Buffer Unavailable
interrupt.
An interrupt timer RIWT (bits 7:0 in Receive Interrupt Watchdog Timer Register
(Table
programmed with a non-zero value, it gets activated as soon as the RxDMA completes a
transfer of a received frame to system memory without asserting the Receive Interrupt
because it is not enabled in the corresponding Receive Descriptor (RDES1[31]. When this
timer runs out as per the programmed value, RI bit is set and the interrupt is asserted if
427) contains all the bits that might cause an interrupt.
431)) is given for flexible control of Receive Interrupt. When this Interrupt timer is
(Table
427). Interrupts are cleared by writing a 1 to the corresponding bit position.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
(Table
(Table
(Table
427) are set HIGH.
(Table
427) for the cause of the interrupt. The interrupt is not
427) indicates that one or more frames were
427) is the (interrupt) status register. The
Table
428. In such conditions, the receive
Chapter 22: LPC18xx Ethernet
Table 429
UM10430
© NXP B.V. 2011. All rights reserved.
contains an
(Table
526 of 1164
429).