LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 262

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
15.6.4.1 Pin interrupts
15.6.4.2 Group interrupts
15.6.5 Recommended practices
With group interrupts, any subset of the pins in each port can be selected to contribute to
a common interrupt. Any of the pin and port interrupts can be enabled to wake the part
from Deep-sleep mode or Power-down mode.
In this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin Interrupt
Select registers (PINTSEL0-7). All of the other Pin Interrupt registers contain 8 bits,
corresponding to the pins called out by the PINTSEL0-7 registers. The PINTMODE
register defines whether each interrupt pin is edge- or level-sensitive. The PINTRISE and
PINTFALL registers detect edges on each interrupt pin, and can be written to clear (and
set) edge detection. The PINTST register indicates whether each interrupt pin is currently
requesting an interrupt, and PINTST can be written to clear interrupts.
The other pin interrupt registers play different roles for edge-sensitive and level-sensitive
pins, as described in
Table 193. Pin interrupt registers for edge- and level-sensitive pins
In this interrupt facility, an interrupt can be requested for each port, based on any selected
subset of pins within each port. The pins that contribute to each port interrupt are selected
by 1s in the port’s Enable register, and an interrupt polarity can be selected for each pin in
the port’s Polarity register. The level on each pin is exclusive-ORed with its polarity bit and
the result is ANDed with its enable bit, and these results are then inclusive-ORed among
all the pins in the port, to create the port’s raw interrupt request.
The raw interrupt request from each of the two group interrupts is sent to the NVIC, which
can be programmed to treat it as level- or edge-sensitive (see
The following lists some recommended uses for using the GPIO port registers:
Name
PINTEN_R
PINTSEN_R
PINTCEN_R
PINTEN_F
PINTSEN_F
PINTCEN_F
•
•
•
•
•
•
For initial setup after Reset or re-initialization, write the PORT registers.
To change the state of one pin, write a Byte Pin or Word Pin register.
To change the state of multiple pins at a time, write the SET and/or CLR registers.
To change the state of multiple pins in a tightly controlled environment like a software
state machine, consider using the NOT register. This can require less write operations
than SET and CLR.
To read the state of one pin, read a Byte Pin or Word Pin register.
To make a decision based on multiple pins, read and mask a PORT register.
All information provided in this document is subject to legal disclaimers.
Table
Rev. 00.13 — 20 July 2011
Write to enable rising-edge interrupts.
Write to disable rising-edge interrupts. Write to disable interrupts.
Enables falling-edge interrupts.
Write to enable falling-edge interrupts. Write to select high-active.
Edge-sensitive function
Enables rising-edge interrupts.
Write to disable falling-edge interrupts. Write to select low-active.
193.
Level-sensitive function
Enables interrupts.
Write to enable interrupts.
Selects active level.
Chapter 15: LPC18xx GPIO
Section
UM10430
6.8).
© NXP B.V. 2011. All rights reserved.
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