LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 434

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
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User manual
turn off the transceiver clock putting the system in to the disconnect-suspend state. Since
software cannot depend on the presents of a clock to clear the Suspend bit, a wake-up
event must be defined which would clear the Suspend bit and allow the transceiver clock
to resume.
The device can also go into suspend mode as a result of a suspend command from the
host. Suspend is signaled on the bus by 3ms of idle time on the bus. This will generate a
suspend interrupt to the software at which point the software must prepare to go into
suspend then set the suspend bit. Once the Suspend bit is set the transceiver clock may
turn off and the device will be in the suspended state. The device has two ways of getting
out of suspend.
In either case the system designer must insure an orderly restoration of the power and
clocks to the suspended circuitry.
1. If remote wake-up is enabled, a wake-up event could be defined which would clear
2. If the host puts resume signaling on the bus, it will clear the Suspend bit and generate
the Suspend bit. The software would then initiate the resume by setting the Resume
bit in the port controller then waiting for a port change interrupt indicating that the port
is in an operational state.
a port change interrupt when the resume is finished.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
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